DocumentCode
1814829
Title
Design of a high-speed Reed-Solomon decoder
Author
Baek, Jae H. ; Kang, Jin Y. ; Sunwoo, Myung H.
Author_Institution
Sch. of Electr. & Comput. Eng., Ajou Univ., Suwon, South Korea
Volume
5
fYear
2002
fDate
2002
Abstract
This paper proposes a Reed-Solomon (RS) decoder for applications that require high-speed data communication and reliability. The proposed architecture can support variable n and k values (37\n\n\t\t
Keywords
Reed-Solomon codes; circuit CAD; circuit simulation; decoding; digital signal processing chips; error correction; high-speed integrated circuits; integrated circuit design; integrated circuit modelling; integrated circuit reliability; logic CAD; systolic arrays; 0.5 micron; 3.3 V; 640 Mbit/s; 80 MHz; Chien search algorithm; Euclid block latency; Forney algorithm; RS decoder; clock cycles; data reliability; data transfer rate; decoder architecture; decoder operating frequency; decoder supply voltage; error correction; high-speed Reed-Solomon decoder; high-speed data communication; latency reduction; modified Euclid algorithm; parallel processing architecture; symbol errors; systolic arrays; Clocks; Data communication; Decoding; Delay; Error correction; Libraries; Parallel processing; Reed-Solomon codes; Systolic arrays; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on
Print_ISBN
0-7803-7448-7
Type
conf
DOI
10.1109/ISCAS.2002.1010823
Filename
1010823
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