A finite element modeling of dynamic hot spot effects in MOSFET dies due to voiding in the solder die-attach

Author

Katsis, D.C. ; VanWyk, J.D.

Author_Institution

US Army Res. Lab., Adelphi, MD, USA

Volume

2

fYear

2003

fDate

15-19 June 2003

Firstpage

828

Abstract

Large area die-attach defects have been shown to increase the thermal impedance of power semiconductor devices. Further observations have shown hotspots in the silicon die due to voids in the die-attach. Experimental measurements for devices with various levels of die-attach void growth are presented This data is then correlated with finite element thermal modeling to improve the estimate of peak die temperature for voided semiconductor devices.

Keywords

elemental semiconductors; finite element analysis; power MOSFET; semiconductor device models; silicon; temperature measurement; thermal analysis; voids (solid); MOSFET dies; die-attach void growth; dynamic hot spot effects; finite element modeling; finite element thermal modeling; peak die temperature estimation; power semiconductor devices; solder die-attach increase; thermal impedance; voided semiconductor devices; voiding; Capacitance; Conducting materials; Finite element methods; MOSFET circuits; Power semiconductor devices; Semiconductor device packaging; Semiconductor materials; Silicon; Temperature measurement; Temperature sensors;

fLanguage

English

Publisher

ieee

Conference_Titel

Power Electronics Specialist Conference, 2003. PESC '03. 2003 IEEE 34th Annual

ISSN

0275-9306

Print_ISBN

0-7803-7754-0

Type

conf

DOI

10.1109/PESC.2003.1218164

Filename

1218164