Title :
Exploiting hardware reconfigurability on window join
Author :
Fukuda, Eric S. ; Kawashima, Hitoshi ; Inoue, H. ; Asai, Tetsuya ; Motomura, Masato
Author_Institution :
Grad. Sch. of Inf. Sci. & Technol., Hokkaido Univ., Sapporo, Japan
Abstract :
Stream processing is attracting wider attention in recent years, and in order to get high efficiency, more people are now trying to leverage hardware for stream processing. In this paper, we clarify two issues by taking window join as an example application: (a) how a software engineer would efficiently utilize hardware, and (b) how adaptiveness will be achieved on it. We use a dynamically reconfigurable hardware with a C-based high level synthesis tool as our evaluation platform. The throughput improved by 216 times through software code optimization, and achieved 26 times higher throughput/power efficiency than an optimized software solution for a CPU. We conclude that a software engineer with certain hardware knowledge will be able to facilitate hardware, and dynamic reconfiguration capability improves the throughput/power efficiency of stream processing.
Keywords :
C language; high level synthesis; reconfigurable architectures; C-based high-level synthesis tool; CPU; dynamically reconfigurable hardware; power efficiency improvement; software code optimization; stream processing; throughput efficiency improvement; window join; Computer architecture; Educational institutions; Field programmable gate arrays; Hardware; Optimization; Software; Throughput; high level synthesis; processor architecture; stream processing; window join;
Conference_Titel :
High Performance Computing and Simulation (HPCS), 2013 International Conference on
Conference_Location :
Helsinki
Print_ISBN :
978-1-4799-0836-3
DOI :
10.1109/HPCSim.2013.6641496