Fast, exploration of ΔΣADC design space

Author

Bajdechi, O. ; Huijsing, J.H. ; Gielen, G.

Author_Institution

Delft Univ. of Technol., Netherlands

Volume

2

fYear

2002

fDate

2002

Abstract

An algorithm used to rapidly evaluate performance of delta-sigma (ΔΣ) analog-to-digital converters (ADC) is presented. The algorithm browses through a set of orders of the converter, numbers of cascaded loops and numbers of bits and decides if a goal dynamic range (DR) can be achieved in a given range of oversampling ratio (OSR) values. The decision of validity of a proposed solution is based on a method to estimate the DR of a converter by Z-domain (polynomial) calculus. The entire design space exploration takes less than 10 minutes of runtime on a 1-GHz computer and is used to select all possible candidates for further (manual or automatic) optimization.

Keywords

analogue-digital conversion; circuit CAD; circuit optimisation; delta-sigma modulation; polynomials; Z-domain polynomial calculus; delta-sigma analog-to-digital converter; design space exploration; dynamic range; optimization algorithm; oversampling ratio; Circuit noise; Databases; Distortion; Polynomials; Signal to noise ratio; Space exploration; Time domain analysis; Topology; Transfer functions; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on

Conference_Location

Phoenix-Scottsdale, AZ

Print_ISBN

0-7803-7448-7

Type

conf

DOI

10.1109/ISCAS.2002.1010921

Filename

1010921