Stochastic analysis of stable marriages in combined input output queued switches

Output queued switches with N input and output ports require up to N serial memory operations per time slot (taken to be the time between packet arrivals at an input). Given the high and increasing processor/memory gap, it is important to shift the bottleneck from memory to processor in order to obtain scalable architectures. It has recently been demonstrated that most output queued switches can be emulated using combined input output queued switches which require O(N) processor operations and a small, constant number of memory operations, thus moving the performance bottleneck from memory to processor. These bounds hold against all, even adversarial, traffic patterns. We analyze the scheduling algorithms used by Chuang et al. (1999) and Prabhakar et al. to obtain the above results when the input traffic is stochastic. We prove that if the queue size at each output port in the output queued switch being emulated has an exponential tail, then the above algorithms need just O(logN) processor operations with high probability