Title :
A CMOS signed multiplier using wave pipelining
Author :
Nguyen, V.D. ; Liu, W. ; Gray, C.T. ; Cavin, R.K.
Author_Institution :
Dept. of Electr. & Comput. Eng., North Carolina State Univ., Raleigh, NC, USA
Abstract :
The authors present a high-performance 8 × 8 CMOS signed multiplier using the wave pipelining technique. The multiplier architecture is based on the modified Booth algorithm and Wallace-Tree techniques. At the transistor level, a biased CMOS gate is used to balance the path delays; it provides a means of postprocess tuning, even though it has a disadvantage in power consumption. The multiplier is implemented with MOSIS 2-μm technology, and simulation results show a tenfold speed-up over nonpipelined operation
Keywords :
multiplying circuits; 2 micron; ASIC; CMOS signed multiplier; MOSIS; Wallace-Tree techniques; biased CMOS gate; high-performance; modified Booth algorithm; postprocess tuning; wave pipelining; Application specific integrated circuits; Clocks; Computer architecture; Decoding; Latches; Logic; Pipeline processing; Propagation delay; Signal processing algorithms; Timing;
Conference_Titel :
Custom Integrated Circuits Conference, 1993., Proceedings of the IEEE 1993
Conference_Location :
San Diego, CA
Print_ISBN :
0-7803-0826-3
DOI :
10.1109/CICC.1993.590699
