Title :
A 300-MHz, 16-bit, 0.5-μm BiCMOS digital signal processor core LSI
Author :
Nomura, Masahiro ; Yamashina, Masakazu ; Goto, Junichi ; Inoue, Toshiaki ; Suzuki, Kazwnasa ; Motomura, Masato ; Koseki, Youichi ; Shih, Benjamin S. ; Horiuchi, Tadahiko ; Hamatake, Nobuhisa ; Kumagai, Kouichi ; Enomoto, Tadayoshi ; Yamada, Hachiro
Author_Institution :
NEC Corp., Kanagawa, Japan
Abstract :
A 300-MHz, 16-bit, 0.5-μm BiCMOS digital signal processor (DSP) core LSI, which employs a parallel processing architecture, 300-MHz redundant binary arithmetic units, and a sophisticated high-performance electrical design, has been developed for video signal processing. Measured clock skew and critical path delay are less than 80 ps and 2.6 ns, respectively. It has a parallel processing architecture capable of discrete cosine transform (DCT) operations for efficient motion picture coding in video signal processing
Keywords :
BiCMOS digital integrated circuits; 0.5 micron; 16 bit; 300 MHz; BiCMOS digital signal processor core LSI; DCT operations; clock skew; critical path delay; efficient motion picture coding; high-performance electrical design; parallel processing architecture; redundant binary arithmetic units; video signal processing; BiCMOS integrated circuits; Clocks; Digital arithmetic; Digital signal processing; Digital signal processors; Discrete cosine transforms; Large scale integration; Parallel processing; Signal design; Video signal processing;
Conference_Titel :
Custom Integrated Circuits Conference, 1993., Proceedings of the IEEE 1993
Conference_Location :
San Diego, CA
Print_ISBN :
0-7803-0826-3
DOI :
10.1109/CICC.1993.590702
