Parallel VLSI architectures for a class of LDPC codes

Author

Kim, Sungwook ; Sobelman, Gerald E. ; Moon, Jaekyun

Author_Institution

Dept. of Electr. & Comput. Eng., Minnesota Univ., Minneapolis, MN, USA

Volume

2

fYear

2002

fDate

2002

Abstract

This paper presents high-performance encoder and decoder architectures for a class of low density parity check (LDPC) codes. The codes considered here are based on the parallelly concatenated parity check encoder structure. A major advantage of these codes is that the generator matrix and the parity check matrix are both sparse, which leads to efficient VLSI implementations for the encoder and the decoder. Our designs use 6-bit quantization with a code rate of 8/9 and a block size of 576 bits. An evaluation of the speed and hardware complexity is given, and simulation results for the bit error rate are obtained

Keywords

VLSI; concatenated codes; decoding; error statistics; integrated circuit design; parallel architectures; quantisation (signal); sparse matrices; LDPC codes; VLSI architectures; bit error rate; decoder architecture; generator matrix; low density parity check codes; parallel architectures; parallelly concatenated parity check encoder; parity check matrix; quantization; Computer architecture; Concatenated codes; Decoding; Electronic mail; Hardware; Moon; Parity check codes; Sparse matrices; Turbo codes; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on

Conference_Location

Phoenix-Scottsdale, AZ

Print_ISBN

0-7803-7448-7

Type

conf

DOI

10.1109/ISCAS.2002.1010932

Filename

1010932