DocumentCode
1816447
Title
Digital filter design for compact on-chip oversampling A/D conversion
Author
Mar, Monte F. ; Brodersen, Robert W.
Author_Institution
EECS Dept., California Univ., Berkeley, CA, USA
fYear
1993
fDate
9-12 May 1993
Abstract
High-level design tools and architecture libraries have been developed for the analysis and design of digital decimation filters for oversampling A/D (analog-to-digital) converters. Results from a 14-bit signal acquisition module designed with these tools are presented. The chip was optimized for a decimation ratio of 256, a sampling rate of 20 kHz, a passband extending to 9 kHz with less than 0.2 dB of ripple, and 65 dB of out-of-band attenuation
Keywords
analogue-digital conversion; ASIC; architecture libraries; compact on-chip; digital decimation filters; digital filter design; high-level design tools; oversampling A/D conversion; signal acquisition module; speech acquisition; standard CMOS; Algorithm design and analysis; Application specific integrated circuits; Digital filters; Digital modulation; Finite impulse response filter; IIR filters; Signal design; Signal processing algorithms; Signal resolution; Software libraries;
fLanguage
English
Publisher
ieee
Conference_Titel
Custom Integrated Circuits Conference, 1993., Proceedings of the IEEE 1993
Conference_Location
San Diego, CA
Print_ISBN
0-7803-0826-3
Type
conf
DOI
10.1109/CICC.1993.590719
Filename
590719
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