A 200 MHz CMOS digital radio frequency memory chip with analog output

A single-chip architecture which realizes most of the intermediate-frequency (IF) part of a digital radio frequency memory (DRFM) is presented. The implementation in CMOS technology (Lnom = 1 μm), called the DRFMC, allows different modes of operation with 200-MHz clock frequency (400-MHz nominal). The modes are pulsed signal synthesis, delay line, or continuous-wave (CW) synthesis. The DRFMC is programmable via a DMA interface. A digital signal processing unit and a digital-to-analog converter have been included. The output is analog and digital, which supports cascading of several DRFMCs