Test preparation methodology for high coverage of physical defects in CMOS digital ICs

The constant increase of IC circuit complexity and quality requirements make high quality testing a difficult challenge. In this work, a methodology for test preparation leading to high physical defect coverage is proposed. Two new software tools are presented, that implement the proposed methodology, tabloid and iceTgen. From the gate level schematics, a heuristic is proposed to generate a list of pseudo-realistic faults that, when used as target faults for test pattern generation, lead to high coverage of physical defects with a shorter test sequence than the one generated using realistic faults extracted from the layout