Performance-driven compaction for analog integrated circuits

Author

Felt, Eric ; Malavasi, E. ; Charbon, Edoardo ; Totaro, R. ; Sangiovanni-Vincentelli, A.

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA

fYear

1993

fDate

9-12 May 1993

Abstract

The authors describe a novel approach to the layout compaction of analog integrated circuits which observes all of the performance and technology constraints necessary to guarantee proper analog circuit functionality. The approach consists of two stages: a fast constraint graph critical path algorithm followed by a general linear programming algorithm. Circuit performance is guaranteed by mapping high-level performance constraints to low-level bounds on parasitics and then to minimum spacing constraints between adjacent nets. The algorithm has been implemented and found to display remarkable completeness and efficiency

Keywords

circuit layout CAD; ASIC; CMOS circuits; adjacent nets; analog integrated circuits; fast constraint graph critical path algorithm; general linear programming algorithm; high-level performance constraints; layout compaction; low-level bounds; mapping; minimum spacing constraints; parasitics; performance-driven compaction; routing; Analog circuits; Analog computers; Circuit optimization; Circuit topology; Compaction; Constraint optimization; Integrated circuit interconnections; Iterative algorithms; Linear programming; Routing;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 1993., Proceedings of the IEEE 1993

Conference_Location

San Diego, CA

Print_ISBN

0-7803-0826-3

Type

conf

DOI

10.1109/CICC.1993.590738

Filename

590738