A one-million-circuit CMOS ASIC logic family

Author

Gregor, Raul ; Ng, C. ; Libous, J. ; Carter, E. ; Beaudoin, R. ; Chu, A. ; Grindel, D. ; Kinney, J. ; Lee, M. ; Mentes, L. ; Oppold, J. ; Russell, M. ; Secor, A. ; Yenik, G.

Author_Institution

IBM Technology Products, Essex Junction, VT, USA

fYear

1993

fDate

9-12 May 1993

Abstract

Metallization and device channel length enhancements to an existing 0.5-μm CMOS process are exploited in the design of a high-density ASIC (application-specific integrated circuit) logic family. Wired circuit density exceeds one-million equivalent two-input NANDs, with typical gate delays of 250 ps at 3.3 V. A total of 17 different chip sizes are offered, along with several surface-mount package options. Both IBM and industry-standard design systems are supported, along with a cost effective LSSD-based test methodology

Keywords

CMOS logic circuits; 0.5 micron; 250 ps; 3.3 V; CMOS ASIC logic family; IBM design systems; LSSD-based test methodology; compilable embedded arrays; cost effective; device channel length enhancements; gate delays; high-density; industry-standard design; metallisation; multi-port register arrays; one-million equivalent two-input NANDs; one-million-circuit ASIC family; single-port SRAM; standard cell architectron; surface-mount package options; Application specific integrated circuits; CMOS logic circuits; CMOS process; Circuit testing; Costs; Delay; Integrated circuit metallization; Integrated circuit packaging; Logic design; Logic devices;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 1993., Proceedings of the IEEE 1993

Conference_Location

San Diego, CA

Print_ISBN

0-7803-0826-3

Type

conf

DOI

10.1109/CICC.1993.590753

Filename

590753