0.3 μm mixed analog/digital CMOS technology for low-voltage operation

A 0.3-μm mixed analog/digital CMOS technology for low-voltage operation is developed, including a novel MOSFET structure with laterally doped buried (LDB) layer and a low-voltage-coefficient double-polysilicon capacitor. The LDB-structure MOSFET enables constant threshold voltage independent of channel-length fluctuation due to the fabrication process, which is indispensable for precise analog-circuits operation at low voltage. It also enables high current drivability which is 10% above that of a conventional structure and low junction capacitance which is less than half that in a conventional structure. The double-polysilicon capacitor, whose insulator thickness is scaled down (oxide-equivalent 20 nm), reduces the capacitor area and achieves a voltage coefficient which is 1/10 that of a conventional capacitor by introducing arsenic ion implantation to the interface between the top polysilicon plate and the insulator