A pipelined front-end, timing and amplitude digitizing system

A front-end digitizing system is needed forract- the straw tracking-detector of the MECO experiment. This detector has 24,000 channels of time and amplitude readout, and operates in a high singles count-rate environment. This system continuously digitizes the incoming pulses of every channel, using a latency buffer to temporarily hold all digitized information. Channel occupancy information for each event is also sent to a local external logic analyzer, and can become part of the trigger decision. All the stored data in the latency buffer is read with zero-suppression to local RAM upon presentation of a valid trigger. The system can be self-triggered or triggered by a coincidence of the internal occupancy signal with an external gate. The data readout provides sub-nanosecond timing and 6-8 bit amplitude resolution, and the system clock can be varied between 15-75 MHz. This design will be implemented in an ASIC due to the large number of readout channels, the requirement initial parallel data flow due to the high single rates, and the number of memory buffers. The digitizer is to be controlled by a FPGA. This paper presents the conceptual design of this system. We anticipate that the ASIC can be used for many other applications requiring the acquisition of time and waveform signals in high counting rate environments, such as PET, CZT, or other HEP experiments.