DocumentCode :
1817410
Title :
An efficient modeling codec architecture for binary shape coding
Author :
Liu, Tzu-Ming ; Shieh, Bai-Jue ; Lee, Chen-Yi
Author_Institution :
Inst. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Volume :
2
fYear :
2002
fDate :
2002
Abstract :
In this paper, the efficient modeling codec architecture for binary shape coding is presented. This novel design includes a memory unit that employs the address generation module and the select-and-barrel shift module to speed up the process of border pixels generation. A simple architecture of the modified modeling unit, which uses a column-scan map to reduce the number of mux and barrel shifters is proposed. Based on the proposed architecture, it deals not only with context computation of the intra mode but also of the inter mode on the same hardware architecture. In addition, this design technique is suitable for the context-based arithmetic encode/decode in the whole MPEG-4 codec system
Keywords :
binary codes; image coding; video codecs; video coding; MPEG-4 codec system; address generation module; binary shape coding; border pixels generation; column-scan map; context-based arithmetic encode/decode; design technique; hardware architecture; inter mode context computation; intra mode context computation; memory unit; modeling codec architecture; modified modeling unit; select-and-barrel shift module; Arithmetic; Codecs; Computer architecture; Decoding; Hardware; Image coding; MPEG 4 Standard; Shape; Video coding; Video compression;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on
Conference_Location :
Phoenix-Scottsdale, AZ
Print_ISBN :
0-7803-7448-7
Type :
conf
DOI :
10.1109/ISCAS.2002.1010988
Filename :
1010988
Link To Document :
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