IDDQ test results on a digital CMOS ASIC

The test program of a digital CMOS ASIC (application-specific integrated circuit) was instrumented for IDDQ current measurement. The design test included a low-fault-coverage functional set of vectors as well as high-fault-coverage scan set of vectors. Analysis of current distributions of parts failing and passing vector sets provides insight into the potential of static current testing. Many issues remain, but the data suggest that real quality improvements can be obtained from implementing static current testing on a small subset of device vectors