VLSI architecture design and implementation for TWOFISH block cipher

Author

Lai, Yeong-Kang ; Chen, Liang-Gee ; Lai, Jian-Yi ; Parng, Tai-Ming

Author_Institution

Dept. of Electr. Eng., Nat. Chung-Hsing Univ., Taichung, Taiwan

Volume

2

fYear

2002

fDate

2002

Abstract

A novel VLSI architecture of the TWOFISH block cipher is presented. Based on the loop-folding technique combined with efficient hardware mapping, the architecture can make data encryption/decryption more efficient and secure. To demonstrate the correctness of our design, a prototype chip for the architecture has been implemented by using 0.35 μm CMOS technology. The chip can achieve an encryption rate of 200 Mb/s and consume 44 mW while operating at a 66 MHz clock rate. Therefore, the chip can be applied to on-line encryption in high-speed networking protocols like ATM networks.

Keywords

CMOS integrated circuits; VLSI; asynchronous transfer mode; cryptography; integrated circuit design; packet switching; protocols; telecommunication networks; 0.35 micron; 200 Mbit/s; 44 mW; 66 MHz; ATM networks; CMOS technology; TWOFISH block cipher; VLSI architecture design; VLSI architecture implementation; clock rate; computer systems; data encryption/decryption; data security; efficient hardware mapping; encryption rate; high-speed networking protocols; loop-folding; on-line encryption; power consumption; Application software; CMOS technology; Cryptography; Databases; Flow graphs; Hardware; High-speed networks; Protection; Prototypes; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on

Conference_Location

Phoenix-Scottsdale, AZ

Print_ISBN

0-7803-7448-7

Type

conf

DOI

10.1109/ISCAS.2002.1010998

Filename

1010998