DocumentCode
1817697
Title
A high precision (+/- 100 ppm) CMOS clock generator for optimum sampling of analog RGB data [in LCD panel display]
Author
Terukina, A. ; Nozawa, T. ; Suzuki, Y. ; Hino, A. ; Koyama, S. ; Moritani, A.
Author_Institution
IBM Japan, Ltd., Kanagawa, Japan
fYear
1993
fDate
9-12 May 1993
Abstract
An integrated timing generator composed of variable delay line and PLL (phase-locked-loop) is described. To determine the sampling point for video analog data, a pixel clock is regenerated from an H-synchronous signal with higher stability (±100 ppm) and the clock edge is adjusted to cover a 40 nsec cycle by 2.2 nsec per step. It is important to minimize the noise effect on the variable delay line and PLL in order to realize the higher stability. The circuit technique and measured data are presented. The resulting ±100 ppm oscillation stability illustrates the benefits of this circuit technique
Keywords
phase locked loops; CMOS clock generator; LCD flat panel; PLL; analog RGB data; high precision; integrated timing generator; noise effect; optimum sampling; pixel clock; variable delay line; video analog data; Cathode ray tubes; Circuit stability; Clocks; Delay lines; Frequency; Image sampling; Phase locked loops; Signal generators; Signal resolution; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
Custom Integrated Circuits Conference, 1993., Proceedings of the IEEE 1993
Conference_Location
San Diego, CA
Print_ISBN
0-7803-0826-3
Type
conf
DOI
10.1109/CICC.1993.590803
Filename
590803
Link To Document