DocumentCode
1817739
Title
CMOS sampler with 1 Gbit/s bandwidth and 25 ps resolution
Author
van Noije, W. ; Gray, C.T. ; Liu, W. ; Hughes, T.A. ; Cavin, R.K. ; Farlow, W.J.
Author_Institution
Dept. of Electr. & Comput. Eng., North Carolina State Univ., Raleigh, NC, USA
fYear
1993
fDate
9-12 May 1993
Abstract
A technique and circuitry for real-time high-resolution sampling of a digital waveform are presented. This circuitry has been fabricated in 1.2 μm CMOS technology, and test results show a bandwidth of up to 1 Gbit/s for the digital data and a sampling resolution externally adjustable between 25 ps and 250 ps. The fabricated circuit has shown sampling stability, monotonicity, and uniformity in sampling resolution
Keywords
signal sampling; 1 Gbit/s; 1.2 micron; 25 to 250 ps; CMOS sampler; biased inverters; bistable latch; differential inverter; digital waveform; monotonicity; real-time high-resolution sampling; sampling resolution; sampling stability; uniformity; Bandwidth; CMOS technology; Circuits; Clocks; Inverters; Latches; Metastasis; Propagation delay; Sampling methods; Signal resolution;
fLanguage
English
Publisher
ieee
Conference_Titel
Custom Integrated Circuits Conference, 1993., Proceedings of the IEEE 1993
Conference_Location
San Diego, CA
Print_ISBN
0-7803-0826-3
Type
conf
DOI
10.1109/CICC.1993.590806
Filename
590806
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