DocumentCode :
1817834
Title :
Design for mitigation of single event effects
Author :
Nicolaidis, Michael
Author_Institution :
iRoC Technol., Grenoble, France
fYear :
2005
fDate :
6-8 July 2005
Firstpage :
95
Lastpage :
96
Abstract :
Various fault tolerant techniques can be employed to mitigate SEUs, SETs and SELs. However, such techniques usually inquire high hardware, speed and power penalty that most commercial applications could not afford. This presentation concerns low cost mitigation techniques for single-event effects induced by alpha particles and atmospheric neutrons in advanced nanometric designs.
Keywords :
fault tolerance; integrated circuit design; integrated circuit reliability; nanoelectronics; neutron effects; alpha particles; atmospheric neutrons; fault tolerance; fault tolerant techniques; integrated circuit design; integrated circuit reliability; low cost mitigation techniques; nanoelectronics; nanometric designs; neutron effects; single event effects; single event transients; single event upsets; Clocks; Error analysis; Latches; Logic devices; Logic gates; Neutrons; Pulse circuits; Silicon; Single event upset; Thyristors;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
On-Line Testing Symposium, 2005. IOLTS 2005. 11th IEEE International
Print_ISBN :
0-7695-2406-0
Type :
conf
DOI :
10.1109/IOLTS.2005.20
Filename :
1498137
Link To Document :
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