Title :
An enhanced successive-approximation circuit for A/D conversion
Author :
Webster, Christopher M. ; Comer, Donald T.
Author_Institution :
Pennsylvania State Univ., Harrisburg, Middletown, PA, USA
Abstract :
A modified successive approximation A/D (analog-to-digital) converter is introduced which employs parallel analog comparators to reduce the number of compare cycle from N to N/s for an N-bit digital code. Unlike the case of traditional flash/successive-approximation techniques, the additional comparators have a very low accuracy requirements and in general can be designed using digital, rather than analog, design rules and techniques. Using a predictive approximation approach it is not unreasonable to expect a 40% decrease in total cycle time, including logic delays, compared to a conventional successive-approximation converter
Keywords :
analogue-digital conversion; A/D conversion; CMOS process; digital code; enhanced successive-approximation circuit; high-speed comparators; number of compare cycle; parallel analog comparators; predictive approximation approach; prototype circuit; Analog-digital conversion; Bismuth; Clocks; Complexity theory; Computational geometry; Fabrication; Logic circuits; Logic devices; Neodymium; Voltage;
Conference_Titel :
Custom Integrated Circuits Conference, 1993., Proceedings of the IEEE 1993
Conference_Location :
San Diego, CA
Print_ISBN :
0-7803-0826-3
DOI :
10.1109/CICC.1993.590811
