On jitter due to delay cell mismatch in DLL-based clock multipliers

This paper describes the jitter problem in DLL-based clock multipliers that arises due to stochastic mismatch in the delay cells that are used in the voltage controlled delay line of the DLL. An analysis is presented that relates the stochastic spread of the delay of the cells to the output jitter of the clock multiplier. This analysis shows that relative time deviations are highest in the middle of the delay line and proportional to the square root of the frequency multiplication factor of the structure. A circuit design technique, called impedance level scaling, is presented that allows the designer to optimize the noise and mismatch behavior of a circuit independent from other specifications such as speed and linearity. Applying this technique on delay cell design yields a direct trade-off between noise induced jitter and power usage, and between stochastic mismatch induced jitter and power usage