Title :
A low-voltage low-power fast-settling operational amplifier for use in high-speed high-resolution pipelined A/D converters
Author :
Lotfi, Reza ; Shoaei, Omid
Author_Institution :
Dept. Electr. & Comput. Eng., Tehran Univ., Iran
Abstract :
The most power-hungry circuit in a high-speed high-resolution pipelined analog-to-digital converter is the first stage opamp. In this paper a 1.5 V two-stage opamp is proposed which uses the cascode compensation to achieve a bandwidth higher than the miller compensation and also a class-A/AB output stage to reduce the high current needed in the opamp second stage to satisfy the slew-rate performance. HSPICE simulations show that considerable power is saved merging these two techniques in a 0.25 μm CMOS process.
Keywords :
CMOS analogue integrated circuits; SPICE; analogue-digital conversion; integrated circuit design; integrated circuit modelling; low-power electronics; operational amplifiers; pipeline processing; 0.25 micron; 1.5 V; CMOS low-voltage fast-settling operational amplifiers; CMOS process; HSPICE simulations; amplifier bandwidth; analog to digital converters; cascode compensation; class-A/AB output stage; first stage opamp; high-resolution ADC; high-speed pipelined ADC; low power op-amp; miller compensation; opamp second stage current reduction; power saving techniques; slew-rate performance; two-stage opamp; Analog circuits; Bandwidth; Capacitors; Computational modeling; Dynamic range; Dynamic voltage scaling; Energy consumption; High power amplifiers; Operational amplifiers; Power engineering and energy;
Conference_Titel :
Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on
Conference_Location :
Phoenix-Scottsdale, AZ
Print_ISBN :
0-7803-7448-7
DOI :
10.1109/ISCAS.2002.1011013
