Power-balanced self checking circuits for cryptographic chips

Cryptographic chips are highly susceptible to fault injection and power analysis attacks, which easily lets an attacker gain secret keys intended to be secure. In addition to these issues, testability circuitry is frequently manipulated to induce faults and undesired behavior. When power-balanced dual-rail (1-of-2) logic, a return-to-spacer protocol and power-balanced totally self checking checkers with redundant transistors are used together, they significantly improve and enforce security; simultaneously facilitating secure on-line testability. In this paper, we propose and show how to implement such circuits in cryptographic chips, the fruits of which are high reliability, testability and security.