Title :
Design of a self checking Reed Solomon encoder
Author :
Cardarilli, G.C. ; Pontarelli, S. ; Re, M. ; Salsano, A.
Author_Institution :
Dept. of Electron. Eng., Rome "Tor Vergata" Univ., Italy
Abstract :
In this paper, an innovative self-checking Reed Solomon encoder architecture is described. The presented architecture exploits some properties of the arithmetic operations in GF(23) related to the parity of the binary representation of the field elements. Moreover, a method for introducing self-checking capabilities on all the arithmetic structures used in the Reed Solomon encoder is presented. Finally the self-checking encoder architecture has been mapped on a FPGA evaluating its area overhead.
Keywords :
Reed-Solomon codes; arithmetic codes; built-in self test; field programmable gate arrays; parity check codes; FPGA; GF(23); Reed Solomon encoder; arithmetic operation; arithmetic structures; binary representation; self-checking encoder architecture; Arithmetic; Circuit faults; Decoding; Electrical fault detection; Error correction codes; Fault detection; Field programmable gate arrays; Galois fields; Polynomials; Reed-Solomon codes;
Conference_Titel :
On-Line Testing Symposium, 2005. IOLTS 2005. 11th IEEE International
Print_ISBN :
0-7695-2406-0
DOI :
10.1109/IOLTS.2005.21
