Design of a self checking Reed Solomon encoder

In this paper, an innovative self-checking Reed Solomon encoder architecture is described. The presented architecture exploits some properties of the arithmetic operations in GF(2³) related to the parity of the binary representation of the field elements. Moreover, a method for introducing self-checking capabilities on all the arithmetic structures used in the Reed Solomon encoder is presented. Finally the self-checking encoder architecture has been mapped on a FPGA evaluating its area overhead.