Title :
Hot-carrier reliability design guidelines for CMOS logic circuits
Author :
Quader, Khandker N. ; Minami, Eric R. ; Huang, Wei-Jen ; Ko, Ping K. ; Hu, Chenming
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
Abstract :
Generalized hot-carrier-reliability design rules that translate device-level degradation to CMOS circuit lifetime are presented. The design rules, which consist of two factors, speed and time, and which include both PMOSFET and NMOSFET models, can roughly predict CMOS circuit lifetime and can also aid circuit designers in evaluating the hot-carrier sensitivity of different circuit blocks. For an operating frequency of 50 MHz, the NMOSFET and PMOSFET speed factors are 120 and 350, respectively, and the speed factors with respect to saturation drain current changes are 4 and 2, respectively
Keywords :
CMOS logic circuits; CMOS logic circuits; NMOSFET models; PMOSFET models; circuit lifetime; device-level degradation; hot-carrier sensitivity; hot-carrier-reliability design rules; speed factors; time factors; CMOS logic circuits; Circuit simulation; Degradation; Frequency; Guidelines; Hot carriers; MOSFET circuits; Predictive models; Ring oscillators; Stress;
Conference_Titel :
Custom Integrated Circuits Conference, 1993., Proceedings of the IEEE 1993
Conference_Location :
San Diego, CA
Print_ISBN :
0-7803-0826-3
DOI :
10.1109/CICC.1993.590831
