Design of on-line testing for SoC with IEEE P1500 compliant cores using reconfigurable hardware and scan shift

In this paper, a new design for online testing of system on a chip (SoC) is presented. The proposed method is based on usage of the available IEEE P1500 architecture and a small embedded FPGA core. Our method has a little additional routing overhead of the SoC, which keeps its performance much higher than conventional approaches. The design of this method is easy and it does not make a burden on the system designer. The error latency has an order of only few minutes in worst case scenario. We present the hardware implementation of this method and evaluate its performances.