Test generation methodology for high-speed floating point adders

High performance real number operations in embedded processors´ and microprocessors´ datapaths are realized by floating point (FP) arithmetic units. FP units have a complex structure which although consisting of classic integer arithmetic components faces serious testability problems due to the limited accessibility of the components from the FP unit ports. In this paper we present a test generation methodology for FP adders based on the high-speed, two-path architecture. The key feature of the presented methodology is the identification of testability conditions that guarantee effective test pattern application and fault propagation for each of the components of the FP adder. According to our test methodology, the testability conditions guide test generation process. The identified test conditions are independent of the internal structure and the size of the components. Thus, they can be applied to floating point adders of various exponent and significand sizes built with components of different architectures.