3DV — An embedded, dense stereovision-based depth mapping system

Author

Camellini, Gabriele ; Felisa, Mirko ; Medici, Paolo ; Zani, Paolo ; Gregoretti, Francesco ; Passerone, Claudio ; Passerone, Roberto

Author_Institution

VisLab -Dipt. di Ing. dell´Inf., Univ. di Parma, Parma, Italy

fYear

2014

fDate

8-11 June 2014

Firstpage

1435

Lastpage

1440

Abstract

This paper describes the architecture and hardware implementation of an embedded, low-cost and low-power dense stereo reconstruction system, running at 30 fps at VGA resolution. The processing pipeline includes an initial image rectification stage, a cost generation unit based on the non-parametric census transform, a state-of-the-art Semi-Global cost optimization stage, and a final minimization and noise suppression step. The hardware implementation is based on a Xilinx Zynq^TM System-on-Chip, which besides the FPGA provides a physical dual-core ARM CPU, which is exploited for control and to deliver output over the integrated Gigabit Ethernet connection.

Keywords

computer vision; field programmable gate arrays; image reconstruction; image resolution; minimisation; stereo image processing; system-on-chip; transforms; 3DV; FPGA; VGA resolution; Xilinx ZynqTM system-on-chip; cost generation unit; dense stereo reconstruction system; dense stereovision-based depth mapping system; initial image rectification stage; integrated gigabit Ethernet connection; minimization step; noise suppression step; nonparametric census transform; physical dual-core ARM CPU; processing pipeline; semiglobal cost optimization stage; Field programmable gate arrays; Hardware; Image reconstruction; Pipelines; Registers; Table lookup; Transforms;

fLanguage

English

Publisher

ieee

Conference_Titel

Intelligent Vehicles Symposium Proceedings, 2014 IEEE

Conference_Location

Dearborn, MI

Type

conf

DOI

10.1109/IVS.2014.6856563

Filename

6856563