Dynamic fault test and diagnosis in digital systems using multiple clock schemes and multi-VDD test

Performance test is a powerful technique to identify difficult to detect defects. Recently, the authors have shown that multi-VDD test schemes may be used in a BIST environment to simulate multi-clock test. Using circuit and logic-level fault simulation it has been demonstrated that the effect of lowering VDD on the propagation delay time, while keeping invariant the observation pace at speed test, is similar to the effect of decreasing the clock period t_CLK while keeping nominal VDD. In this paper, a simple analytical model to represent the dependence of propagation delay time variations of logic elements, Δ_pd on depleted VDD (i.e., on ΔVDD) is introduced. The model allows to back-annotate this dependence to logic-level fault simulation. As clock period decreases (or VDD decreases) failing vectors inducing errors are identified. Performance histograms, describing the dependence of the number of failing vectors on higher clock speed (or lower VDD) are used for delay fault detection and defect diagnosis. Basic infrastructures, ISCAS benchmarks and a combinational block of an industrial fleet management system, XTRAN, is used to demonstrate the results.