Title :
Solving a graph layout problem using strictly digital neural networks with virtual slack-neurons
Author :
Murakami, Katsuhiko ; Nakagawa, Tohru
Author_Institution :
Dept. of Inf. & Control Eng., Toyota Technol. Inst., Nagoya, Japan
Abstract :
This paper presents a neural network parallel algorithm for minimizing edge crossings in drawings of nonplanar subgraphs using strictly digital neural networks enhanced with virtual slack-neurons (SDNN/V). The problem is relevant to the design of printed circuits, where special wiring arrangements have to be made when crossings occur. The proposed algorithm finds the minimum number of crossings or on approximation thereof and also provides a liner embedding realizing the number of crossings found. The problem can be defined as a “set selection problem”. The results of solving the graph layout problem using a simulator of SDNN/V show that the computation time in parallel execution only requires three steps to derive one of near-optimum solutions. We present a numbering method for neurons in order of importance within each constraint satisfaction set. The paper shows that the numbering method has improved the quality of solutions by up to 50%
Keywords :
circuit layout CAD; graph theory; neural nets; printed circuit manufacture; circuit layout problem; edge crossings; graph layout; parallel algorithm; parallel processing; printed circuit design; strictly digital neural networks; virtual slack-neurons; wiring arrangements; Computational modeling; Concurrent computing; Control engineering; Engineering drawings; Neural networks; Neurons; Parallel algorithms; Planarization; Printed circuits; Wiring;
Conference_Titel :
Neural Networks, 1999. IJCNN '99. International Joint Conference on
Conference_Location :
Washington, DC
Print_ISBN :
0-7803-5529-6
DOI :
10.1109/IJCNN.1999.831581