High speed communications links for ASICs

Summary form only given. ASIC integration and speeds have risen rapidly in the past couple of years to the point now where 50 to I00 MHz clock rates and hundreds of thousands of used gates are commonplace. These performance and integration levels place huge demands on chip-to-chip data transfer and packaging, with communications rates of up to 1 Gbit/sec being required. The author compares some of the traditional I/O standards available to an ASIC designer such as TTL, CMOS with some of the more recent advances such as PECL, GTL, and LVDS. Design considerations and limitations of these modern schemes are explored