DocumentCode
1819166
Title
Power efficient chip-to-chip signaling schemes
Author
Farzan, Kamran ; Johns, David A.
Author_Institution
Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada
Volume
2
fYear
2002
fDate
2002
Abstract
In low voltage signaling for chip-to-chip digital communication, noise is a crucial factor and since common-mode noise is prevalent on matched printed circuit board (PCB) traces, differential signaling is an effective method for chip-to-chip communication. However, it needs two signal paths for transmitting one bit. Multi-level signaling can be used to reduce the number of required signal paths for transmitting one bit. To reduce the required signal power, this paper investigates several coding schemes for this application. A novel scheme, which improves the performance of ordinary 4-level pulse amplitude modulation (PAM) by roughly 3 dB, is proposed. Finally a low complexity method for an analog implementation of this scheme is presented
Keywords
analogue processing circuits; circuit noise; digital communication; low-power electronics; modulation coding; printed circuits; pulse amplitude modulation; 4-level PAM; 4LINE-PAM6 scheme; LV signaling; analog implementation; chip-to-chip digital communication; chip-to-chip signaling schemes; coding schemes; common-mode noise; differential signaling; low complexity method; low voltage signaling; matched PCB traces; multi-level signaling; power efficient signaling schemes; printed circuit board traces; pulse amplitude modulation; Bit error rate; Cables; Circuit noise; Electromagnetic interference; Modulation coding; Noise level; Pulse modulation; Redundancy; Semiconductor device noise; Transmitters;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on
Conference_Location
Phoenix-Scottsdale, AZ
Print_ISBN
0-7803-7448-7
Type
conf
DOI
10.1109/ISCAS.2002.1011049
Filename
1011049
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