Title :
A nor-type MLC ROM with novel sensing scheme for embedded applications
Author :
Sung, Star ; Chang, Thomas ; Chen, JueiLung
Author_Institution :
Taiwan ImagingTek Corp., Taiwan
Abstract :
3 bits per cell nor-type MLC ROM, multi layer cell read only memory macro of 4M bits density is presented. The MLC ROM is designed by a 0.18 μm CMOS logic process. The ROM cell of 0.80μm × 0.90μm with 0.05μm per step of the channel width and channel length increase is determined to obtain 16 levels of Ids. A scheme of 2-step sensing with current-to-voltage converter (step1) and an ADC (step2) are applied to obtain an access time of 10 ns.
Keywords :
CMOS logic circuits; analogue-digital conversion; logic design; memory architecture; read-only storage; 0.05 micron; 0.18 micron; 0.80 micron; 0.90 micron; 10 ns; 4 Mbit; CMOS logic process; analog-to-digital converter; current-to-voltage converter; embedded applications; multilayer cell read only memory; nor-type MLC ROM; sensing scheme; CMOS logic circuits; CMOS process; Communication system control; Digital signal processing; Digital signal processing chips; Engines; Logic design; Multimedia communication; Random access memory; Read only memory;
Conference_Titel :
Memory Technology, Design, and Testing, 2005. MTDT 2005. 2005 IEEE International Workshop on
Conference_Location :
Taipei
Print_ISBN :
0-7695-2313-7
DOI :
10.1109/MTDT.2005.11
