• DocumentCode
    1819316
  • Title

    A novel single poly-silicon EEPROM using trench floating gate

  • Author

    Wu, Meng-Yi ; Feng, Shin-Chang ; King, Ya-Chin

  • Author_Institution
    Dept. of Electr. Eng., National Tsing-Hua Univ., Hsinchu, Taiwan
  • fYear
    2005
  • fDate
    5-5 Aug. 2005
  • Firstpage
    35
  • Lastpage
    37
  • Abstract
    A single poly-silicon trench gate-type EEPROM, SPTG, featuring low voltage operation and fast programming is proposed. Using a trench floating gate instead of the stack gate structure, this cell is suitable for embedded application. The trenched floating gate (FG) combining with a deep-N-well implanted region guarantees high coupling ratio for CHEI programming and source side FN erasing operation. This cell array in a NOR-type array features fast random access capacity and IIF 2 cell size.
  • Keywords
    EPROM; logic gates; CHEI programming; NOR-type array; deep-n-well implanted region; embedded application; erasing operation; single poly-silicon EEROM; stack gate structure; trench floating gate; CMOS logic circuits; CMOS process; EPROM; Electronic mail; Implants; Laboratories; Logic programming; Low voltage; Silicon; Voltage control;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Memory Technology, Design, and Testing, 2005. MTDT 2005. 2005 IEEE International Workshop on
  • Conference_Location
    Taipei
  • ISSN
    1087-4852
  • Print_ISBN
    0-7695-2313-7
  • Type

    conf

  • DOI
    10.1109/MTDT.2005.13
  • Filename
    1498200
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1819316