Title :
An investigation into three-level ferroelectric memory
Author :
Raiter, Kamlesh R. ; Cockburn, Bruce F.
Author_Institution :
Dept. of Electr. & Comput. Eng., Alberta Univ., Edmonton, Alta., Canada
Abstract :
Ferroelectric random-access memory (FeRAM) is an emerging nonvolatile memory technology that has several key advantages over flash memory, including much greater program-erase endurance and much faster write speed. However, FeRAM array storage capacities currently lag behind those of flash memory by more than three orders of magnitude; consequently, FeRAM has so far tended to be used only in niche applications, such as smart cards and electronic metering. Significant increases in FeRAM storage density requires progress on many technical fronts. Most digital memory technologies use two possible data signal levels to encode one bit per storage cell. Multilevel cell flash memory uses four data signal levels to increase the storage density to two bits per cell. In this paper we report the results of a preliminary study that investigated the possibility of using three data signal levels to increase the array storage density from 1 bit per cell to an average of 1.5 bits per cell. The principal challenge is to ensure the accurate writing of the three signal states (ferroelectric film polarized in the "up" and "down" directions, and a depolarized film) and the reliable sensing of cell states in the presence of noise and inevitable device parameter variations.
Keywords :
ferroelectric storage; flash memories; random-access storage; array storage capacities; data signal levels; digital memory technologies; ferroelectric random-access memory; flash memory; multilevel cells; multilevel signaling; nonvolatile memory; program-erase endurance; storage density; ternary memory; ternary signaling; write speed; CMOS technology; Electronic mail; Ferroelectric films; Ferroelectric materials; Flash memory; Flash memory cells; Material storage; Nonvolatile memory; Polarization; Random access memory; ferroelectric memory; multilevel cells; multilevel signaling; ternary memory; ternary signaling;
Conference_Titel :
Memory Technology, Design, and Testing, 2005. MTDT 2005. 2005 IEEE International Workshop on
Conference_Location :
Taipei
Print_ISBN :
0-7695-2313-7
DOI :
10.1109/MTDT.2005.17