• DocumentCode
    1819455
  • Title

    Full-speed field programmable memory BIST supporting multi-level looping

  • Author

    Du, Xiaogang ; Mukherjee, Nilanjan ; Cheng, Wu-Tung ; Reddy, Sudhakar M.

  • Author_Institution
    Mentor Graphics, Wilsonville, OR, USA
  • fYear
    2005
  • fDate
    5-5 Aug. 2005
  • Firstpage
    67
  • Lastpage
    71
  • Abstract
    A full-speed field-programmable memory BIST controller is proposed. The proposed instruction and architecture designs enable full-speed operation of algorithms containing more than one level of looping.
  • Keywords
    built-in self test; integrated memory circuits; programmable circuits; built-in self-test; field programmable memory BIST controller; multilevel looping; Algorithm design and analysis; Built-in self-test; Failure analysis; Fault detection; Manufacturing; Production; Programmable control; Random access memory; System-on-a-chip; Testing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Memory Technology, Design, and Testing, 2005. MTDT 2005. 2005 IEEE International Workshop on
  • Conference_Location
    Taipei
  • ISSN
    1087-4852
  • Print_ISBN
    0-7695-2313-7
  • Type

    conf

  • DOI
    10.1109/MTDT.2005.25
  • Filename
    1498205
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1819455