DocumentCode
1819639
Title
DFT techniques for memory macro with built-in ECC
Author
Kushida, Keiichi ; Otsuka, Nobuaki ; Hirabayashi, Osamu ; Takeyama, Yasuhisa
Author_Institution
SoC R&D Center, Toshiba Corp., Kawasaki, Japan
fYear
2005
fDate
5-5 Aug. 2005
Firstpage
109
Lastpage
114
Abstract
DFT techniques to implement ECC circuitry on memory macro with no additional test cost are proposed. New methodology to design a Hamming code matrix is used to achieve whole ECC system testing with standard memory BIST and conventional test sequence. The proposed ECC techniques are implemented in a 512Kb SRAM macro and demonstrated by hardware characterization with 90nm technology.
Keywords
Hamming codes; SRAM chips; built-in self test; design for testability; error correction codes; integrated circuit testing; 512 kbit; 90 nm; DFT techniques; ECC system testing; Hamming code matrix; SRAM macro; built-in error correcting code; built-in self-test; design for testability; memory BIST; test sequence; Built-in self-test; Circuit testing; Code standards; Costs; Design for testability; Design methodology; Error correction codes; Hardware; Random access memory; System testing;
fLanguage
English
Publisher
ieee
Conference_Titel
Memory Technology, Design, and Testing, 2005. MTDT 2005. 2005 IEEE International Workshop on
Conference_Location
Taipei
ISSN
1087-4852
Print_ISBN
0-7695-2313-7
Type
conf
DOI
10.1109/MTDT.2005.19
Filename
1498212
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