Design and implementation of error detection and correction circuitry for multilevel memory protection

Traditional memories use only two levels per cell (0/1), which limits their storage capacity to 1 bit per cell. By doubling the cell capacity, we increase the density of the memory at the expense of its reliability. There are several types of memories that employ multi-level techniques. The subject of this paper is the design of a multi-level dynamic random access memory (MLDRAM). The problem of its reliability is investigated and a practical solution is proposed. The solution is based on the organization of the error-correcting code (ECC) that is tuned to the MLDRAM implementation. Conventional memories employ single-error-correcting and double-error-detecting (SEC-DED) ECCs. While such codes have been considered for MLDRAMs, their use is inefficient, due to likely double-bit errors in a single cell. For this reason, we propose an induced ECC architecture that uses ECC in such a way that no common error corrupts two bits. Induced ECC allows a significant increase in the reliability of the MLDRAM, by making use of improved check-bit generation circuitry that allows us to use less space for the parity-bit generation circuitry. The suggested approach is able to correct a two-bit error in a two-bits-per-cell MLDRAM, which the basic ECC cannot correct. The proposed solutions make the MLDRAM more tolerant to any kind of fault, and consequently more practical for mass production