Measurement and characterization of 6T SRAM cell current

Despite that there are many works discussing the parameter variations in 6T SRAM bit cells, most of them are based on Monte-Carlo simulations. Basic performance indices, such as cell current, are rarely obtained from measurements. In this paper, we present a simple circuit design to directly measure the cell current. To explore the physical location dependency, the bit cells are selected at the boundary and in the interior of a sub-array, and for each bit cell, the cell currents are measured by two sides as in opposite states. The means and standard deviations of the cell current distributions are given at 1.8V/25°C, 1.5V/25°C, and 1.8V/85°C. Empirical power-law relationships are then derived to model the cell currents and their mismatch as a function of threshold voltage and supply voltage. Our results have important implications in both design and manufacturing of highspeed and low-power SRAMs.