• DocumentCode
    1819863
  • Title

    Multiple-valued logic-in-memory VLSI based on ferroelectric capacitor storage and charge addition

  • Author

    Kimura, Hiromitsu ; Hanyu, Takahiro ; Kameyama, Michitaka

  • Author_Institution
    Graduate Sch. of Inf. Sci., Tohoku Univ., Sendai, Japan
  • fYear
    2002
  • fDate
    2002
  • Firstpage
    161
  • Lastpage
    166
  • Abstract
    A multiple-valued logic-in-memory VLSI using ferroelectric capacitors is proposed to realize an arithmetic-oriented VLSI with real-time programmable capacitor storage. The use of a remnant-polarization charge on a ferroelectric capacitor makes it possible to perform not only a real-time programmable storage function but also a linear-sum function, thereby resulting in a compact hardware while maintaining a high-speed processing capability. As a design example, a full adder with a storage capability is evaluated. Its performance is superior to that of a corresponding binary CMOS implementation
  • Keywords
    VLSI; adders; charge injection; digital arithmetic; ferroelectric capacitors; ferroelectric storage; integrated logic circuits; integrated memory circuits; multivalued logic circuits; polarisation; programmable logic devices; real-time systems; adder performance; arithmetic-oriented VLSI; binary CMOS implementation; charge addition; compact hardware; ferroelectric capacitors; high-speed processing capability; linear-sum function; multiple-valued logic-in-memory VLSI; real-time programmable capacitor storage; remnant-polarization charge; Adders; Capacitors; Circuits; Ferroelectric materials; Iron; MOSFETs; Nonvolatile memory; Polarization; Very large scale integration; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Multiple-Valued Logic, 2002. ISMVL 2002. Proceedings 32nd IEEE International Symposium on
  • Conference_Location
    Boston, MA
  • Print_ISBN
    0-7695-1462-6
  • Type

    conf

  • DOI
    10.1109/ISMVL.2002.1011085
  • Filename
    1011085