Title :
Multiple-valued-digit number representations in arithmetic circuit algorithms
Author_Institution :
Dept. of Inf. Eng., Nagoya Univ., Japan
Abstract :
Multiple-valued-digit number representations, i.e., positional weighted number representations with a digit set consisting of more than two values, are often used in arithmetic circuit algorithms for high-speed and/or area efficient computation. These algorithms may be implemented by a multiple-valued logic more efficiently than by the binary logic. This article shows how these number representations are used in arithmetic circuit algorithms
Keywords :
digital arithmetic; multivalued logic; multivalued logic circuits; area efficient computation; arithmetic circuit algorithms; binary logic; digit set; high-speed computation; multiple-valued logic; multiple-valued-digit number representations; positional weighted number representations; Acceleration; Algorithm design and analysis; Arithmetic; Circuits; Logic;
Conference_Titel :
Multiple-Valued Logic, 2002. ISMVL 2002. Proceedings 32nd IEEE International Symposium on
Conference_Location :
Boston, MA
Print_ISBN :
0-7695-1462-6
DOI :
10.1109/ISMVL.2002.1011093