A VLSI architecture for a frequency-agile single-chip 10-MBaud digital QAM modulator

An architecture for VLSI implementation of an all-digital frequency-agile single-chip quadrature amplitude modulation (QAM) modulator with a continuously-variable symbol rate and intermediate frequency (IF) has been investigated. The proposed chip architecture accommodates a variable IF center frequency up to 70 MHz and a programmable symbol rate from a few kHz up to 10 MHz. The single-chip modulator consists of a square-root Nyquist filter, two halfband filters to cancel the images from upsampling, a variable interpolator to accommodate continuously selectable symbol rates, and a frequency translator. This paper discusses the architecture techniques used to achieve a 200 MHz throughput rate in a modest CMOS technology