Thermal optimization for micro-architectures through selective block replication

Increased power densities result to higher on-chip temperatures, which in turn creates numerous problems tightly firmed to reliability issues. This problem is expected to become even more severe for deep-submicron technologies. In this paper, we propose a thermal-aware exploration framework at the microarchitecture level for temperature hotspots elimination through selective resource replication. Experimental results based on the LEON3 processor synthesized with a 45 nm technology library, shown that the proposed methodology leads to designs with fewer hotspots, while the maximal temperatures at these hotspots are also reduced. Specifically, temperature reduction of 17 Kelvin degrees is feasible, which leads to improvement against aging phenomena about 14%, with a controllable overhead in silicon area about 15%, as compared to conventional architecture design.