Architecture design space exploration of run-time scalable issue-width processors

Reconfigurable chip multiprocessors realizing very long instruction word (VLIW) processors of dynamically-scalable issue width enable resource-aware adaptation to diverse processing requirements. The execution performance of such clustered VLIW processors is significantly influenced by different design parameters of the fundamental processing cores. In this paper we present a design space exploration addressing the following design parameters: the register file size, number of issue slots, inter cluster move bandwidth, and latency. We thereby investigate the quantitative performance impact of each parameter as well their interdependency for 18 benchmarks of different processing domains. Our results show that the cluster configuration significantly influences the processing performance: the performance loss compared to theirs unclustered architectures can be as low as 2% but also may exceed 100%.