Fully source-coupled logic based multiple-valued VLSI

Author

Ike, Tsukasa ; Hanyu, Takahiro ; Kameyama, Michitaka

Author_Institution

Dept. of Comput. & Math. Sci., Tohoku Univ., Sendai, Japan

fYear

2002

fDate

2002

Firstpage

270

Lastpage

275

Abstract

A novel source-coupled logic (SCL) style using multiple-valued signals, called multiple-valued source-coupled logic (MVSCL), which operates with an input voltage swing of about 0.3 V is proposed for high-speed and low-power VLSI systems. A multiple-valued comparator which is a key component, is realized by using differential-pair circuits (DPCs), so that its power dissipation can be greatly reduced while maintaining high-speed switching. Moreover, the current-source control allows steady current flow to cut off when the circuit is not active, thereby saving power dissipation. A 54×54-bit signed-digit multiplier based on MVSCL is designed in a 0.35 μm CMOS technology, and its performance is superior to both corresponding binary static CMOS and multiple-valued current-mode (MVCM) implementation

Keywords

CMOS logic circuits; VLSI; comparators (circuits); integrated logic circuits; multivalued logic; multivalued logic circuits; CMOS technology; MVSCL; differential-pair circuits; high-speed and low-power VLSI; high-speed switching; input voltage swing; multiple-valued VLSI; multiple-valued comparator; multiple-valued signals; multiple-valued source-coupled logic; power dissipation; signed-digit multiplier; Arithmetic; CMOS logic circuits; CMOS technology; Circuit synthesis; Logic circuits; Logic design; Power dissipation; Switching circuits; Very large scale integration; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Multiple-Valued Logic, 2002. ISMVL 2002. Proceedings 32nd IEEE International Symposium on

Conference_Location

Boston, MA

Print_ISBN

0-7695-1462-6

Type

conf

DOI

10.1109/ISMVL.2002.1011098

Filename

1011098