Proceedings 20th IEEE VLSI Test Symposium (VTS 2002)

fYear

2002

fDate

2-2 May 2002

Abstract

The following topics are dealt with: microprocessor test; very low voltage testing; DFT testers; test set compression techniques; analog BIST; slow speed testing; test automation; scan-based testing; burn-in reduction; test power; fault diagnosis; analog circuit testing; high level test techniques; SoC test; supply current testing; IEEE P1500; test pattern generation; tester hardware modelling; FPGA test; fault modeling; memory testing; test-cost reduction; and oscillation based test.

Keywords

IEEE standards; analogue integrated circuits; application specific integrated circuits; automatic test pattern generation; boundary scan testing; built-in self test; data compression; fault diagnosis; fault simulation; field programmable gate arrays; high level synthesis; integrated circuit reliability; integrated circuit testing; logic testing; low-power electronics; DFT; FPGA test; IEEE P1500; SoC test; analog BIST; analog circuit testing; burn-in reduction; fault diagnosis; fault modeling; high level test techniques; memory testing; microprocessor test; oscillation based test; scan-based testing; slow speed testing; supply current testing; test automation; test pattern generation; test power; test set compression; test-cost reduction; tester hardware modelling; very low voltage testing; Analog integrated circuits; Application specific integrated circuits; Boundary scan testing; Data compression; Fault diagnosis; Field programmable gate arrays; High-level synthesis; IEEE standards; Integrated circuit reliability; Integrated circuit testing; Logic circuit testing; Self-testing;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Test Symposium, 2002. (VTS 2002). Proceedings 20th IEEE

Conference_Location

Monterey, CA, USA

Print_ISBN

0-7695-1570-3

Type

conf

DOI

10.1109/VTS.2002.1011102

Filename

1011102