• DocumentCode
    1820355
  • Title

    Scan Islands - a scan partitioning architecture and its implementation on the Alpha 21364 processor

  • Author

    Bhavsar, Dilip K. ; Davies, Richard A.

  • fYear
    2002
  • fDate
    2002
  • Firstpage
    16
  • Lastpage
    21
  • Abstract
    The paper presents a pragmatic scan partitioning architecture that allows less than perfect scan design in high performance, VLSI circuits to cost-effectively achieve test development and manufacturing test goals. The paper then describes an implementation of the architecture on Compaq´s Alpha 21364 microprocessor.
  • Keywords
    VLSI; boundary scan testing; integrated circuit testing; logic partitioning; logic testing; microprocessor chips; production testing; Compaq Alpha 21364 processor; VLSI circuits; manufacturing test goals; scan islands; scan partitioning architecture; test development goals; Automatic control; Automatic test pattern generation; Centralized control; Circuit testing; Computer aided manufacturing; Computer architecture; High performance computing; Microprocessors; Pins; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Test Symposium, 2002. (VTS 2002). Proceedings 20th IEEE
  • Print_ISBN
    0-7695-1570-3
  • Type

    conf

  • DOI
    10.1109/VTS.2002.1011105
  • Filename
    1011105
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1820355