• DocumentCode
    1820486
  • Title

    Scan-path with directly duplicated and inverted duplicated registers

  • Author

    Goessel, M. ; Singh, A. ; Sogomonyan, E.

  • Author_Institution
    Dept. of Comput. Sci., Univ. of Potsdam, Germany
  • fYear
    2002
  • fDate
    2002
  • Firstpage
    47
  • Lastpage
    52
  • Abstract
    In this paper a systematic scan-path design with duplicated and inverted duplicated memory elements is proposed. Contrary to a known solution (Raina et al., 2000), no additional control lines for additional multiplexors are needed. Full controllability and observability of the proposed scan-path is demonstrated.
  • Keywords
    controllability; logic design; logic testing; observability; sequential circuits; controllability; duplicated memory elements; duplicated registers; inverted duplicated memory elements; inverted duplicated registers; observability; scannable memory elements; sequential circuit design; systematic scan-path design; test vectors; two-rail logic; Circuit testing; Clocks; Controllability; Debugging; Delay; Integrated circuit interconnections; Observability; Registers; Sequential analysis; Sequential circuits;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Test Symposium, 2002. (VTS 2002). Proceedings 20th IEEE
  • Print_ISBN
    0-7695-1570-3
  • Type

    conf

  • DOI
    10.1109/VTS.2002.1011110
  • Filename
    1011110
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1820486